Electrically erasable programmable read only memory (EEPROM) (E.sup.2 PROM) cells are extremely useful as non-volatile storage elements which have the advantage of being modified in-circuit more than one time. The following U.S. Patents assigned to Texas Instruments Incorporated illustrate EEPROM devices: U.S. Pat. Nos. 4,979,004; 5,053,839; 5,045,489; and, 5,045,490.
The basic EEPROM transistor is a 4-terminal device as illustrated in prior art FIG. 1. The terminals INOUT 1, INOUT 2 and CONTROL are comparable to the DRAIN, SOURCE and GATE terminals of a regular metal oxide semiconductor field effect transistor (MOSFET). The long-term memory effect is obtained through the fact that the threshold voltage (V.sub.T) of this MOSFET can be electrically modified by controlling the voltage on the fourth terminal (DIFFUSION).
When a large positive voltage (usually 17 V) is applied to the control input, with respect to the DIFFUSION terminal, the effective V.sub.T of the device is raised (usually to about 5 V). When that same large voltage (programming voltage V.sub.PP) is applied to the DIFFUSION terminal, with respect to the CONTROL input, the effective V.sub.T is lowered (usually to about -2 V). In the first case, the EEPROM device strongly turns into an "enhancement" mode device. In the second case, it effectively turns into a "depletion" mode device.
Over time, the difference in V.sub.T between the two modes may decrease due to drift. As a result, the EEPROM cells are often programmed and read back differentially, i.e. a one-bit memory cell is built using two EEPROM devices. One is programmed by raising the effective V.sub.T, the other one by lowering the effective V.sub.T. The cell is read back out by (differentially) comparing the V.sub.T of both devices. This method is much more reliable than attempting to sense a single V.sub.T, because even when the two V.sub.T 's drift towards each other over time, there usually is at least several tens of milli V difference between them, which can be resolved very reliably by a differential comparator or a latch.
A common way of programming and reading back differential EEPROM cells is illustrated in prior art FIG. 2. To program, the READ line is held low. This disables the cross-coupled latch formed by the top 8 transistors. The DOUT output is forced high. Node A and B (drains of the EEPROM devices) are left floating.
To program a logic 1 into prior art FIG. 2, node D is taken to V.sub.PP (17 V) while node DZ is held at 0 V. This raises the V.sub.T of transistor M2 to approximately 5 V and lowers the V.sub.T of transistor M1 to approximately -2 V.
To program a logic 0, node D is held at 0 V, while node DZ is taken to V.sub.PP. This raises the V.sub.T of M2 to approximately 5 V and lowers the V.sub.T of M2 to approximately -2 V.
In READ mode, nodes D and DZ of prior art FIG. 2 are held at 0 V. The READ line is asserted (taken to a logic high or V.sub.DD, which is normally around 5 V). This enables the cross-coupled latch (which can be seen as back-to-back NAND gates with EEPROM devices at the bottom 1). The side of the latch which has the higher V.sub.T (most "enhancement" mode) EEPROM device, will obviously be strongly biased towards a logic 1, while the other side will be biased towards a logic 0. Hence, when READ is enabled, the latch will correctly read out the programmed data. The differential scheme insures that the data can be reliably resolved, even when the V.sub.T 's of transistors M1 and M2 drift towards each other. During the read operation, both D and DZ are held at ground potential (0 V).
In order to be able to combine a number of EEPROM cells into a larger array, the cell described above with reference to prior art FIG. 2 is often surrounded by additional circuitry as illustrated in prior art FIG. 3. DOUT is now a tri-state output. When READ is a logic 0 (and READZ a logic 1), DOUT is in a high-impedance state. When READ is 1 (and READZ is 0), the cross-coupled latch is activated and DOUT reflects the state of the previous programmed bit.
The high-impedance feature of prior art FIG. 3 is useful in order to combine several basic cells onto one output line (normally all the cells in one column of the EEPROM array). Selecting one specific row of the array is achieved by asserting the particular READ line of that row, while leaving the others at 0.
In prior art FIG. 3, NOR gates N1 and N2 are operated off a different power supply than the rest of the cell, but share ground. They are operated off V.sub.PP, which is a high voltage supply and therefore they are built with high-voltage devices. PROGZ, D and DZ are high-voltage inputs.
When the array cell is not in write mode, V.sub.PP is held at V.sub.DD (5 V) and PROGZ is held at 5 V. D and DZ are either 0 V or 5 V. As a result, both the DIFFUSION and the CONTROL terminals of both EEPROM devices are held at 0 V, which is the normal mode for reading.
In order to write the cell of prior art FIG. 3, V.sub.PP is taken to the programming voltage level (17 V). D and DZ are either 17 V or 0 V (each other's complement) and PROGZ is held at 0 V. READ is held at 0 V and READZ at 5 V. This causes the correct V.sub.T to be programmed into each EEPROM device. PROGZ of unselected rows is V.sub.PP.
Prior art FIG. 4 illustrates an EEPROM array using a traditional EEPROM memory cell such as illustrated in prior art FIG. 3 which is manufactured by Texas Instruments Incorporated in device types SN 77715 and SN 104093.
The prior art cell of FIG. 2 has a disadvantage in that there is not convenient method of measuring the V.sub.T 's of both EEPROM transistors after programming. The capability to measure the V.sub.T 's is important in order to determine the integrity of the programmed data over time. As long as one transistor has a sufficiently higher V.sub.T than the other one (ideally, one device should have positive V.sub.T, or operate in enhancement mode, while the other one has a negative V.sub.T, or operates in depletion mode) correct reading of the data is possible.
It is well-known, however, that over time, the V.sub.T 's of the differential cell tend to drift towards each other, thus compromising the reliability of the programmed data (data retention loss or DRL). In order to guarantee a product that will maintain its programmed data over a long time (e.g. -10 years), it is important to measure the difference in V.sub.T of every cell used in a circuit, before the product is shipped to the customer.
It is conceivable to put a limited number of test structures on a die or on a wafer. Measurement of the V.sub.T 's of these test structures (after programming) could be seen as representative for the whole array. But clearly, this simplified method (the main array cells do not contain measurement circuitry) is inferior, since one or two cells could have inferior programming characteristics, while most other ones are good.
It is accordingly an object of the invention to provide a EEPROM wherein the threshold voltages of each EEPROM cell may be individually measured.
Further objects and benefits of the invention will be apparent to those of ordinary skill in the art having the the benefit of the description and drawings following herein.